How JTAG Works
3. The Technical Stuff (Simplified!)
Alright, let's peek under the hood (but don't worry, we'll keep it relatively painless!). JTAG operates using a Test Access Port (TAP), which is a set of pins on the IC that provide access to the internal scan chains. These pins typically include TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), and optionally TRST (Test Reset).
Data is shifted into the chip via TDI, synchronized by TCK, and shifted out via TDO. The TMS signal controls the state of the TAP controller, which is a state machine that governs the operation of the JTAG interface. By manipulating TMS, you can select different instructions, such as shifting data into a specific scan chain or executing a test sequence.
The real magic lies in the Boundary Scan Register (BSR). This register sits between the chip's core logic and its pins. During normal operation, the BSR is transparent, allowing signals to pass through unaffected. However, in boundary scan mode, the BSR can capture the values present on the pins or drive values onto the pins, enabling testing of the external connections.
Think of it like a train switching yard. Normally, trains (data) flow directly through the yard. But when you want to inspect a train, you divert it onto a special track (scan chain) where you can examine it thoroughly before sending it back on its way. JTAG essentially provides the mechanisms to control these "switches" and "tracks" within the IC.
